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| KS0075 34com/100seg driver & controller for dot matrix lcd introduction KS0075 is a dot matrix lcd driver & controller lsi which is fabricated by low power cmos technology. it can display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format. functions character type dot matrix lcd driver & controller internal driver : 34 common and 100 segment signal output easy interface with 4-bit or 8-bit mpu clock synchronized serial interface 5 x 8 dot matrix possible 6 x 8 dot matrix possible bi-directional shift function all character reverse display display shift per line voltage converter for lcd drive voltage : 13 v max (2 times / 3 times) various instruction functions automatic power on reset features internal memory - character generator rom (cgrom) : 9,600 bits (240 characters x 5 x 8 dot) - character generator ram (cgram) : 64 x 8 bits (8 characters x 5 x 8 dot) - segment icon ram (segram) : 16 x 8 bits (96 icons max.) - display data ram (ddram) : 80 x 8 bits (80 characters max.) low power operation - power supply voltage range : 2.7 5.5 v (vdd) - lcd drive voltage range : 3.0 13.0 v (vdd - v5) cmos process programmable duty cycle : 1/17, 1/33 (refer to table 1.) internal oscillator with an external resistor bare chip available
KS0075 34com/100seg driver & controller for dot matrix lcd table 1. programmable duty cycles 5-dot font width display line duty ratio single-chip operation numbers displayable characters possible icons 1 1/17 1 line of 40 characters 80 2 1/33 2 lines of 40 characters 80 4 1/33 4 line of 20 characters 80 6-dot font width display line duty ratio single-chip operation numbers displayable characters possible icons 1 1/17 1 line of 32 characters 96 2 1/33 2 lines of 32 characters 96 4 1/33 4 line of 16 characters 96 KS0075 34com/100seg driver & controller for dot matrix lcd block diagram ! " # $% &' ( % % ' ( % % )'!! * + , ( - % + . + & & & & / / / / ! ! ! !0 0 0 0 1 1 1 11 1 1 1 $ $ $ $% % % %& & & &0 0 0 0 $ $ $ $% % % %& & & &! ! ! !! ! ! ! 2 , 3 &!! ( &!! 2 ( , 1 ( , 3 3 3 3& & & &0 0 0 03 3 3 34 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 5 5 5 5 4 4 4 4 ' ' ' ' 4 4 4 4 3 3 3 3 & & & & / / / / 3 3 3 34 4 4 4 6 6 6 6- - - -/ / / / 3 3 3 34 4 4 4 6 6 6 6- - - -1 1 1 1 $ $ $ $ $ $ $ $- - - - $ $ $ $ 2 2 2 27 7 7 7 8 8 8 8 90 90 90 90 1 1 1 10 0 0 0 5 5 5 5 ! ! ! ! 3 3 3 3 % % % %: : : : 3 3 3 3 3 , $ $ $ $ ; 9& 9& 9& 9& KS0075 34com/100seg driver & controller for dot matrix lcd pad configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 seg100 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 com33 50 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com0 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 seg67 seg66 seg65 seg64 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 vdd osc2 osc1 reset im ie rs/cs rw/sid e/sclk db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 vss2 v5out2 v5out3 v5 v4 v3 v2 v1 vss1 m m (0, 0) chip size : 7450 x 5340 pad size : 100 x 100 unit : x y KS0075 34com/100seg driver & controller for dot matrix lcd pad location KS0075 34com/100seg driver & controller for dot matrix lcd ! ! ! ! ! ! ! ! ! ! ! ! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! ! ! ! !! ! ! ! ! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! !!!!!!!! ! ! ! !! ! ! ! ! !!!!!!!! !!!!!!!! "!# #!$%&'()!*!+$,-!./!0'(1!.2+!34!/5 KS0075 34com/100seg driver & controller for dot matrix lcd pad description pad (no) input/ output name description interface vdd (51) for logical circuit(+3v,+5v) vss1,vss2 (57,72) -0v(gnd) v1 v5 (79 75) power supply bias voltage level for lcd driving. power supply vci (69) input input voltage to the voltage converter to generate lcd drive voltage(vci = 1.0-4.5v). seg1 seg100 (97-163, 1-33) output segment output segment signal output for lcd drive. lcd com0 com33 (80 96, 34 50) output common output common signal output for lcd drive. lcd osc1,osc2 (53,52) input (osc1), output (osc2) oscillator when use internal oscillator, connect external rf resistor. if external clock is used, connect it to osc1. external resistor/oscillator (osc1) c1,c2 (71,70) input external capacitance input to use the voltage converter(2 times /3 times), these pins must be connected to the external capacitance. external capacitance reset (54) input reset pin initialized to low - ie (56) input select pin of instruction set when ie = "high", instruction set is selected as table 6. when ie = "low", instruction set is selected as table 10. - v5out2(73) output two times converter output the value of vci is converted two times. to use three times converter, the same capacitance as that of c1-c2 should be connected here. v5 capacitance v5out3(74) three times converter output the value of vci is converted three times. v5 KS0075 34com/100seg driver & controller for dot matrix lcd pad description (continued) pad (no) input/ output name description interface im (55) input interface mode selection select interface mode with the mpu. when im = "low" : serial mode, when im = "high" : 4-bit/8-bit bus mode. - rs/cs (58) input register select/ chip select in bus mode, used as register selection input. when rs/cs = "high", data register is selected. when rs/cs = "low", instruction register is selected. in serial mode, used as chip selection input. when rs/cs = "low", selected. when rs/cs = "high", not selected.(low access enable) mpu rw/sid (59) input read write/serial input data in bus mode, used as read/write selection input. when rw/sid = "high", read operation. when rw/sid = "low", write operation. in serial mode, used for data input pin. mpu e/sclk (60) input read write enable/serial clock in bus mode, used as read write enable signal. in serial mode, used as serial clock input pin. mpu db0/sod (61) input output/output data bus 0 bit/serial output data in 8-bit bus mode, used as lowest bi-directional data bit. during 4-bit bus mode, open this pin. in serial mode, used as serial data output pin. if not in read operation, open this pin. mpu db1 db3 (62 64) input. output data bus 1 ~ 7 in 8-bit bus mode, used as low order bi- directional data bus. during 4-bit bus mode or serial mode, open these pins. mpu db4 db7 (65 68) in 8-bit bus mode, used as high order bi- directional data bus. in case of 4-bit bus mode, used as both high and low order. db7 used for busy flag output. during serial mode, open these pins. mpu KS0075 34com/100seg driver & controller for dot matrix lcd function description system interface this chip has all three kinds interface type with mpu : serial, 4-bit bus and 8-bit bus. serial and bus(4-bit/8-bit) is selecte d by im input, and 4-bit bus and 8-bit bus is selected by dl bit in the instruction register. during read or write operation, two 8-bit registers are used. one is data register (dr), the other is instruction register(ir). the data register(dr) is used as temporary data storage place for being written into or read from ddram/cgram/segram, target ram is selected by ram address setting instruction. each internal operation, reading from or writing into ram, is done automatically. hence, after mpu reads dr data, the data in the next ddram/cgram/segram address is transferred into dr automatically. also after mpu writes data to dr, the data in dr is transferred into ddram/cgram/segram automatically. the instruction register(ir) is used only to store instruction code transferred from mpu. mpu cannot use it to read instruction data. to select register, use rs/cs input pin in 4-bit/8-bit bus mode(im = "high") or rs bit in serial mode(im = "low"). table 2. various kinds of operations according to rs and r/w bits. rs r/w operation 0 0 instruction write operation (mpu writes instruction code into ir) 01 read busy flag(db7) and address counter (db0 db6) 1 0 data write operation (mpu writes data into dr) 1 1 data read operation (mpu reads data from dr) busy flag (bf) when bf = "high", it indicates that the internal operation is being processed. so during this time the next instruction cannot be accepted. bf can be read, when rs = low and r/w = high(read instruction operation), through db7 port . before executing the next instruction, be sure that bf is not high. KS0075 34com/100seg driver & controller for dot matrix lcd display data ram (ddram) ddram stores display data of maximum 80 x 8 bits (80 characters). ddram address is set in the address counter (ac) as a hexadecimal number. (refer to fig-1.) fig-1. ddram address 1) display of 5-dot font width character 5-dot 1 line display in the case of 1 line display with 5-dot font, the address range of ddram is 00h 4fh. (refer to fig-2) fig-2. 1-line x 40ch. display ! " KS0075 34com/100seg driver & controller for dot matrix lcd 5-dot 2 line display in the case of 2 line display with 5-dot font, the address range of ddram is 00h 27h, 40h 67h. (refer to fig-3) fig-3. 2-line x 40ch. display (5-dot font width) 66789 :;;<=>>> ?@aabc def gchbij dfdgdc da dd de dh db di dj ea ed ee ef eg 6k>lm:n lo>kpkoq ec eh eb ei ej fa fd fe ?@aabc ff fg fc fh fb fi fj ga def gchbij dfdgdc da dd de dh db di dj ea ed ee ef eg ec eh eb ei ej fa fd fe ff fg fc fh fb fi fj ga r8sp=< @tksp u=spv defgch bij dfdgdc da dd de dh db di dj ea ed ee ef eg ec eh eb ei ej fa fd fe ff fg fc fh fb fi fj ga r8sp=< @tksp 7kwtpv KS0075 34com/100seg driver & controller for dot matrix lcd 5-dot 4 line display in the case of 4 line display with 5-dot font, the address range of ddarm is 00h 13h, 20h 33h, 40h 53h, 60h 73h. (refer to fig-4) fig-4. 4-line x 20ch. display (5-dot font width) ! " ! KS0075 34com/100seg driver & controller for dot matrix lcd 2) display of 6-dot font width character when this device is used in 6-dot font width mode, seg97,seg98,seg99 and seg100 must be open. 6-dot 1 line display in the case of 1 line display with 6-dot font, the address range of ddram is 00h 4fh. (refer to fig-5) fig-5. 1-line x 32ch. display & ) &' $%& $%)' $%& $%)' & ) &' & ) &' ! " ! KS0075 34com/100seg driver & controller for dot matrix lcd 6-dot 2 line display in the case of 2 line display with 6-dot font, the address range of ddram is 00h 27h, 40h 67h. (refer to fig-6) fig-6. 2-line x 32ch. display (6-dot font width) ! ! " KS0075 34com/100seg driver & controller for dot matrix lcd 6-dot 4 line display in the case of 4 line display with 6-dot font, the address range of ddarm is 00h 13h, 20h 33h, 40h 53h, 60h 73h. (refer to fig-7) fig-7. 4-line x 16ch. display (6-dot font width) ! " ! KS0075 34com/100seg driver & controller for dot matrix lcd timing generation circuit timing generation circuit generates clock signals for the internal operations. address counter (ac) address counter(ac) stores ddram/cgram/segram address, transferred from ir. after writing into (reading from) ddram/cgram/segram, ac is automatically increased (decreased) by 1. when rs = "low" and r/w = "high", ac can be read through db0 db6 ports cursor/blink control circuit it controls cursor/blink on/off and black/white inversion at cursor position. lcd driver circuit lcd driver circuit has 34 common and 100 segment signals for lcd driving. data from segram/cgram/cgrom is transferred to 100-bit segment latch serially, which is stored to 100-bit shift latch. when each common is selected by 34-bit common register, segment data also output through segment driver from 100-bit segment latch. in 1-line display mode, com0 com17 have 1/17 duty, and in 2-line or 4-line mode, com0-com33 have 1/33 duty ratio. KS0075 34com/100seg driver & controller for dot matrix lcd cgrom (character generator rom) cgrom has 5 x 8-dot 240 character pattern. (refer to table 3) table 3. cgrom character code table KS0075 34com/100seg driver & controller for dot matrix lcd cgram (character generator ram) cgram has up to 5 x 8-dot 8 characters. by writing font data to cgram, user defined character can be used. (refer to table 4) table 4. relationship between character code(ddram) and character pattern(cgram) 1) 5x8 dot character pattern " # # # # # " $ KS0075 34com/100seg driver & controller for dot matrix lcd 2) 6x8 dot character pattern 1. when be(blink enable bit) = high, blink is controlled by b1 and b0 bit. in displaying 5-dot font width, when b1 = "1", enabled dots of p0 p4 will blink, and when b1 = "0" and b0 = "1", enabled dots in p4 will blink, when b1 = "0" and b0 = "0", blink will not happen. in displaying 6-dot font width, when b1 = "1", enabled dots of p0 p5 will blink, and when b1 = "0" and b0 = "1", enabled dots of p5 will blink, when b1 = "0" and b0 = "0", blink will not happen. 2. "x" : don't care !" #$"%&&'$ ! ( )' $$ "** )' $ ! + !!" , ,-./" &0 & & & & & & & +0 + + + + + + + 1 3 !!" , 4 4 4 4 4 1 3 !!" , 5 KS0075 34com/100seg driver & controller for dot matrix lcd segram (segment icon ram) segram has segment control data and segment pattern data. during 1-line display mode, com0(com17) makes the data of segram enable to display icons. when used in 2/4-line display mode com0(com33) does that. its higher 2-bits are blinking control data, and lower 6-bits are pattern data. (refer to table 5 and fig-8) table 5. relationship between segram address and display pattern 1. b1, b0 : blinking control bit control bit blinking port be b1 b0 5-dot font width 6-dot font width 0 x x no blink no blink 1 0 0 no blink no blink 1 0 1 d4 d5 1 1 x d4 ~ d0 d5 ~ d0 2. s1~s80 : icon pattern on/off in 5-dot font width s1~s96 : icon pattern on/off in 6-dot font width 3. "x" : don't care ! ! " # " # ! " ! " # # ! " # ! " # ! " # ! " # " ! # ! " # " # ! ! " # " # ! " ! " # # " " " " " ! " " " "" "# # ! " # " # # # # # # KS0075 34com/100seg driver & controller for dot matrix lcd fig-8. relationship between segram and segment display $ %&' ( $ $ %&' ( $ KS0075 34com/100seg driver & controller for dot matrix lcd instruction description outline to overcome the speed difference between internal clock of KS0075 and mpu clock, KS0075performs internal operation by storing control information to ir or dr. the internal operation is determined according to the signal from mpu, composed of read/write and data bus. (refer to table 6/10) instruction can be divided largely four kinds, (1) KS0075 function set instructions ( set display methods, set data length, etc.) (2) address set instructions to internal ram (3) data transfer instructions with internal ram (4) others . the address of internal ram is automatically increased or decreased by 1. when ie = "high", KS0075 is operated according to instruction set 1(table 6) and when ie = "low", KS0075 is operated according to instruction set 2(table 10). * note : during internal operation, busy flag (db7) is read high. busy flag check must precede the next instruction. when an mpu program with busy flag(db7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the falling edge of the e signal after the busy flag(db7) goes to low. KS0075 34com/100seg driver & controller for dot matrix lcd (1) instruction description 1 (ie = "high") table 6. instruction set 1 instruction re instruction code description execution time r s r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270 khz) clear display x 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram. and set ddram address to "00h" from ac. 1.53ms return home 0 0 0 0 0 0 0 0 0 1 x set ddram address to "00h" from ac and return cursor to its original position if shifted. the contents of ddram are not changed. 1.53ms power down mode 1 0 0 0 0 0 0 0 0 1 pd set power down mode bit. pd = "1" :power down mode set, pd = "0" :power down mode disable 39 m s entry mode set 0 0 0 0 0 0 0 0 1 i/d s assign cursor moving direction. i/d = "1" : increment, i/d = "0" : decrement and display shift enable bit. s = "1" : make display shift of the enabled lines by the ds4 - ds1 bits in the shift enable instruction. s = "0":display shift disable 39 m s 1 0 0 0 0 0 0 0 1 1 bid segment bi-direction function. bid = "1" : seg100 ? seg1, bid = "0" : seg1 ? seg100. display on/off control 0 0 0 0 0 0 0 1 d c b set display/cursor/blink on/off d = "1" : display on, d = "0" : display off, c = "1" : cursor on, c = "0" : cursor off, b = "1" : blink on, b = "0" : blink off. 39 m s extended function set 1 0 0 0 0 0 0 1 fw b/w nw assign font width, black/white inverting of cursor, and 4-line display mode control bit. fw = "1" : 6-dot font width, fw = "0" : 5-dot font width, b/w = "1" : black/white inverting of cursor enable, b/w = "0" : black/white inverting of cursor disable nw = "1" : 4-line display mode, nw = "0" : 1-line or 2-line display mode. 39 m s KS0075 34com/100seg driver & controller for dot matrix lcd (table 6. continued) instruction re instruction code description execution time r s r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270 khz) cursor or display shift 0 0 0 0 0 0 1 s/c r/l x x cursor or display shift. s/c = "1" : display shift, s/c = "0" : cursor shift, r/l = "1" : shift to right, r/l = "0" : shift to left. 39 m s shift enable 1 0 0 0 0 0 1 ds4 ds3 ds2 ds1 (when dh = "1") determine the line for display shift . ds1 = "1/0": 1st line display shift enable/disable ds2 = "1/0": 2nd line display shift enable/disable ds3 = "1/0": 3rd line display shift enable/disable ds4 = "1/0": 4th line display shift enable/disable. 39 m s scroll enable 1 0 0 0 0 0 1 hs4 hs3 hs2 hs1 (when dh = "0") determine the line for horizontal smooth scroll. hs1 = "1/0" : 1st line dot scroll enable/disable hs2 = "1/0" : 2nd line dot scroll enable/disable hs3 = "1/0" : 3rd line dot scroll enable/disable hs4 = "1/0" : 4th line dot scroll enable/disable. 39 m s function set 0 0 0 0 0 1 dl n re(0) dh rev set interface data length (dl = "1" : 8-bit, dl = "0" : 4-bit), numbers of display line when nw = "0", (n = "1" : 2-line, n = "0" : 1-line), extension register, re("0"), shift/scroll enable dh = "1" : display shift enable dh = "0" : dot scroll enable. reverse bit rev = "1" : reverse display, rev = "0" : normal display. 39 m s 1 0 0 0 0 1 dl n re(1) be 0 set dl, n, re("1") and cgram/segram blink enable (be) be = " 1/0" : cgram/segram blink enable/disable 39 m s KS0075 34com/100seg driver & controller for dot matrix lcd (table 6. continued) instruction re instruction code description execution time r s r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270 khz) set cgram address 0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39 m s set segram address 1 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address in address counter. 39 m s set ddram address 0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39 m s set scroll quantity 1 0 0 1 x sq5 sq4 sq3 sq2 sq1 sq0 set the quantity of horizontal dot scroll. 39 m s read busy flag and address x 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 can be known whether during internal operation or not by reading bf. the contents of address counter can also be read. bf = 1 : busy state, bf = 0 : ready state. 0 m s write data x 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram / cgram / segram). 43 m s read data x 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram / cgram / segram). 43 m s * note : 1. when an mpu program with busy flag(db7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the e signal after the busy flag (db7) goes to low. 2. x : dont care KS0075 34com/100seg driver & controller for dot matrix lcd 1) display clear clear all the display data by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, hence, bring the cursor to the left edge on first line of the display. make entry mode increment (i/d = "1"). 2) return home : (re = 0) return home is cursor return home instruction. set ddram address to "00h" into the address counter. return cursor to its original site and return display to its original status, if shifted. contents of ddram does not change. 3) power down mode set : (re = 1) power down mode enable bit set instruction. pd = "high", it makes KS0075 suppress current consumption except the current needed for data storage by executing next three functions. 1. make the output value of all the com/seg ports vdd 2. make the com/seg output value of extension driver vdd by setting d output to "high" and m output to "low" 3. disable voltage converter to remove the current through the divide resistor of power supply. this instruction can be used as power sleep mode. when pd = "low", power down mode becomes disabled. ' '67 &0 & & & & & & & ' '67 &0 & & & & & & & ' '67 &0 & & & & & & & KS0075 34com/100seg driver & controller for dot matrix lcd 4) entry mode set (re = 0) set the moving direction of cursor and display. i/d : increment / decrement of ddram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. * cgram/segram operates the same as ddram, when read from or write to cgram/segram. when s = "high", after ddram write, the display of enabled line by ds1 - ds4 bits in the shift enable instruction is shifted to the right (i/d = "0") or to the left(i/d = "1"). but it will seem as if the cursor does not move. when s = "low", or ddram read, or cgram/segram read/write operation, shift of display like this function is not performed. (re = 1) set the data shift direction of segment in the application set. bid : data shift direction of segment when bid = "low", segment data shift direction is set to normal order from seg1 to seg100. when bid = "high", segment data shift direction is set to reverse from seg100 to seg1. by using this instruction, the efficiency of application board area can be raised. * the bid setting instruction is recommended to be set at the same time level of function set instruction. * db1 bit must be set to "1". #$ % % % % % % % % #$ % % % % % % % % KS0075 34com/100seg driver & controller for dot matrix lcd 5) display on/off control ( re = 0 ) control display/cursor/blink on/off 1 bit register. d : display on/off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data is remained in ddram. c : cursor on/off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display, but i/d register remains its data. b : cursor blink on/off control bit when b = "high", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. if fosc has 270 khz frequency, blinking has 370 ms interval. when b = "low", blink is off. 6) extended function set ( re = 1 ) fw : font width control when fw = "high", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. the user font, specified in cgram, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost space bit of cgram.(refer to fig-9) when fw = "low", 5-dot font width is set. b/w : black/white inversion enable bit when b/w = "high", black/white inversion at the cursor position is set. in this case c/b bit of display on/off control instruction becomes don't care condition. if fosc has frequency of 270 khz, inversion has 370 ms intervals. nw : 4 line mode enable bit when nw = "high", 4 line display mode is set. in this case n bit of function set instruction becomes don't care condition. & % #$ % % % % % % % % KS0075 34com/100seg driver & controller for dot matrix lcd fig-9. 6-dot font width cgrom/cgram 7) cursor or display shift (re = 0) shift right/left cursor position or display, with out writing or reading of display data, this instruction is used to correct or search display data.(refer to table 7) during 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. in 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. note that display shift is performed simultaneously in all the line enabled by ds1 - ds4 in the shift enable instruction. when displayed data is shifted repeatedly, each line shifted individually. when display shift is performed, the contents of address counter are not changed. during low power consumption mode, display shift may not be performed normally. table 7. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, address counter is decreased by 1 0 1 shift cursor to the right, address counter is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display 6-bit 8 - b i t cgrom character font (5-dot) s p a c e 6-bit 8 - b i t cgram character font (6-dot) (cgrom) (cgram) KS0075 34com/100seg driver & controller for dot matrix lcd 8) shift/scroll enable (re = 1) (dh = 0) hs : horizontal scroll per line enable this instruction makes valid dot shift by a display line unit. hs1, hs2, hs3 and hs4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. if the line in 1-line display mode or the 1st line in 2-line display mode, is to be scrolled set hs1 and hs2 to "high". if the 2nd line scroll is needed in 2-line mode, set hs3 and hs4 to "high". (refer to table 8) (dh = 1) ds : display shift per line enable this instruction selects shifting line to be shifted according to each line mode in display shift right/left instruction. ds1, ds2, ds3 and ds4 indicate each line to be shifted, and each shift is performed individually in each line. if ds1 and ds2 is set to "high" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is not shifted. when only ds1 = "high", only the half of the 1st line is shifted. if all the ds bits (ds1 to ds4) are set to "low" (disable), no display is shifted. table 8. relationship between ds and com signal enable bit enabled common signals during shift description hs1/ds1 com1 com8 the part of display line that corresponds to enabled hs2/ds2 com9 com16 common signal can be shifted. hs3/ds3 com17 com24 hs4/ds4 com25 com32 % % % % KS0075 34com/100seg driver & controller for dot matrix lcd 9) function set (re = 0) dl : interface data length control bit when dl = "high", it means 8-bit bus mode with mpu. when dl = "low", it means 4-bit bus mode with mpu. hence, dl is a signal to select 8-bit or 4-bit bus mode. in 4-bit bus mode, it is required to transfer 4-bit data twice. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", it means 1-line display mode. when n = "high", 2-line display mode is set. when nw = "high", n bit is invalid, it means 4-line mode independent of n bit. re : extended function registers enable bit at this instruction, re must be "low". dh : display shift enable selection bit. when dh = "high", enable display shift per line. when dh = "low", enable smooth dot scroll. this bit can be accessed only when ie pin input is "high". rev : reverse enable bit when rev = "high", all the display data are reversed. i.e., all the white dots become black and black dots become white. when rev = "low", the display mode set normal display. KS0075 34com/100seg driver & controller for dot matrix lcd (re = 1) dl : interface data length control bit when dl = "high", it means 8-bit bus mode with mpu. when dl = "low", it means 4-bit bus mode with mpu. hence, dl is a signal to select 8-bit or 4-bit bus mode. when 4-bit bus mode, it is required to transfer 4-bit data twice. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", 1-line display mode is set. when n = "high", 2-line display mode is set. when nw = "high", n bit is invalid, it means 4-line mode independent of n bit. re : extended function registers enable bit when re = "high", extended function set registers, segram address set registers, bid bit, hs/ds bits of shift/scroll enable instruction and be bits of function set register can be accessed. be : cgram/segram data blink enable bit be =high, makes user font of cgram and segment of segram blinking. the quantity of blink is assigned the highest 2 bit of cgram/segram. 10) set cgram address (re = 0) set cgram address to ac. this instruction makes cgram data available from mpu. 11) set segram address (re = 1) set cgram address to ac. this instruction makes cgram data available from mpu. $ ! 8 5 ' 4 1 / & ! # # $ $ $ $ KS0075 34com/100seg driver & controller for dot matrix lcd 12) set ddram address (re = 0) set ddram address to ac. this instruction makes ddram data available from mpu. in 1-line display mode (n = 0, nw = 0), ddram address is from "00h" to "4fh". in 2-line display mode (n = 1, nw = 0), ddram address in the 1st line is from "00h" to "27h", and ddram address in the 2nd line is from "40h" to "67h". in 4-line display mode (nw = 1), ddram address is from "00h" to "13h" in the 1st line, from "20h" to "33h" in the 2nd line, from "40h" to "53h" in the 3rd line and from "60h" to "73h" in the 4th line. 13) set scroll quantity (re = 1) setting sq5 to sq0, horizontal scroll quantity can be controlled in dot units. (refer to table 9) in this case of KS0075 can show hidden areas of ddram by executing smooth scroll from 1 to 48 dots. table 9. scroll quantity according to hds bits sq5 sq4 sq3 sq2 sq1 sq0 function 000000 no shift 000001 shift left by 1-dot 000010 shift left by 2-dot 000011 shift left by 3-dot :::::: : 101111 shift left by 47-dot 11xxxx shift left by 48-dot KS0075 34com/100seg driver & controller for dot matrix lcd 14) read busy flag & address this instruction shows whether KS0075 is in internal operation or not. if the resultant bf is high, the internal operation is i n progress and you have to wait until bf to be low, which by then the next instruction can be performed. in this instruction the value of address counter can also be read. 15) write data to ram write binary 8-bit data to ddram/cgram/segram. the selection of ram from ddram, cgram, or segram, is set by the previous address set instruction : ddram address set, cgram address set, segram address set. ram set instruction can also determines the ac direction to ram. after write operation, the address is automatically increased/decreased by 1, according to the entry mode. 16) read data from ram read binary 8-bit data from ddram/cgram/segram. the selection of ram is set by the previous address set instruction. if address set instruction of ram is not performed before this instruction, the data that read first is invalid, as the direction of ac is not determined. if ram data is read several times without ram address set instruction before read operation, the correct ram data can be obtained from the second, but the first data would be incorrect, as there is no time margin to transfer ram data. in ddram read operation, cursor shift instruction plays the same role as ddram address set instruction : it also transfer ram data to output data register. after read operation address counter is automatically increased/decreased by 1 according to the entry mode. after cgram/segram read operation, display shift may not be executed correctly. in case of ram write operation, ac is increased/decreased by 1 as in read operation after this. in this time, ac indicates the next address position, but the previous data can only be read by read instruction. a d xy 8zh 8zc 8zg 8zf 8ze 8zd 8za KS0075 34com/100seg driver & controller for dot matrix lcd (2) instruction description 2 (ie = "low") table 10. instruction set 2 instruction re instruction code description execution time r s r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270 khz) clear display x 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram. and set ddram address to "00h" from ac. 1.53ms return home x 0 0 0 0 0 0 0 0 1 x set ddram address to "00h" from ac and return cursor to its original position if shifted. the contents of ddram are not changed. 1.53ms entry mode set x 0 0 0 0 0 0 0 1 i/d s assign cursor moving direction. i/d = "1" : increment, i/d = "0" : decrement. and display shift enable bit. s = "1" :make entire display shift of all lines during ddram write, s = "0":display shift disable 39 m s display on/off control 0 0 0 0 0 0 0 1 d c b set display/cursor/blink on/off d = "1" : display on, d = "0" : display off, c = "1" : cursor on, c = "0" : cursor off, b = "1" : blink on, b = "0" : blink off. 39 m s extended function set 1 0 0 0 0 0 0 1 fw b/w nw assign font width, black/white inverting of cursor, and 4-line display mode control bit. fw = "1" : 6-dot font width, fw = "0" : 5-dot font width, b/w = "1" : black/white inverting of cursor enable, b/w = "0" : black/white inverting of cursor disable nw = "1" : 4-line display mode, nw = "0" : 1-line or 2-line display mode 39 m s cursor or display shift 0 0 0 0 0 0 1 s/c r/l x x cursor or display shift. s/c = 1 : display shift, s/c = 0 : cursor shift, r/l = 1 : shift to right, r/l = 0 : shift to left 39 m s KS0075 34com/100seg driver & controller for dot matrix lcd (table 10. continued) instruction re instruction code description execution time r s r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270 khz) scroll enable 1 0 0 0 0 0 1 hs4 hs3 hs2 hs1 determine the line for horizontal smooth scroll. hs1 = "1/0" : 1st line dot scroll enable/disable hs2 = "1/0" : 2nd line dot scroll enable/disable hs3 = "1/0" : 3rd line dot scroll enable/disable hs4 = "1/0" : 4th line dot scroll enable/disable 39 m s function set 0 0 0 0 0 1 dl n re(0) x x set interface data length dl = "1" : 8-bit, dl = "0" : 4-bit numbers of display line when nw = "0", n = "1" : 2-line, n = "0" : 1-line extension register, re("0"), 39 m s 1 0 0 0 0 1 dl n re(1) be 0 set dl, n, re("1") and cgram/segram blink enable (be) be = " 1/0" : cgram/segram blink enable/disable 39 m s set cgram address 0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39 m s set segram address 1 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address in address counter. 39 m s set ddram address 0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39 m s set scroll quantity 1 0 0 1 x qc5 qc4 qc3 qc2 qc1 qc0 set the quantity of horizontal dot scroll. 39 m s read busy flag and address x 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 can be known whether during internal operation or not by reading bf. the contents of address counter can also be read. bf = 1 : busy state, bf = 0 : ready state. 0 m s write data x 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram / cgram / segram). 43m s read data x 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram / cgram / segram). 43 m s * note : 1. when an mpu program with busy flag(db7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the falling edge of the e signal after the busy flag(db7) goes to low 2. x : dont care KS0075 34com/100seg driver & controller for dot matrix lcd 1) display clear clear all the display data by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, hence, bring the cursor to the left edge on first line of the display. and entry mode is set to increment mode (i/d = "1"). 2) return home return home is cursor return home instruction. set ddram address to "00h" into the address counter. return cursor to its original site and return display to its original status, if shifted. contents of ddram does not change. 3) entry mode set set the moving direction of cursor and display. i/d : increment / decrement of ddram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. * cgram/segram operates identically to the ddram, when reading from or writing to cgram/segram. when s = "high", after ddram write, the entire display of all lines is shifted to the right (i/d = "0") or to the left(i/d = "1"). but it will seem as if the cursor does not moving. when s = "low", or ddram read, or cgram/segram read/write operation, shift of entire display is not performed. &# %& ' ' ' ' ' ' ' ' KS0075 34com/100seg driver & controller for dot matrix lcd 4) display on/off control ( re = 0 ) control display/cursor/blink on/off 1 bit register. d : display on/off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data is remained in ddram. c : cursor on/off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display, but i/d register remains its data. b : cursor blink on/off control bit when b = "high", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. if fosc has 270 khz frequency, blinking has 370 ms interval. when b = "low", blink is off. 5) extended function set ( re = 1 ) fw : font width control when fw = "high", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. the user font, specified in cgram, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost space bit of cgram.(refer to fig-10) when fw = "low", 5-dot font width is set. b/w : black/white inversion enable bit when b/w = "high", black/white inversion at the cursor position is set. in this case c/b bit of display on/off control instruction becomes don't care condition. if fosc has frequency of 270 khz, inversion has 370 ms intervals. nw : 4 line mode enable bit when nw = "high", 4 line display mode is set. in this case n bit of function set instruction becomes don't care condition. $ ' &$ %#$ '$ 8 5 ' 4 1 / & ! KS0075 34com/100seg driver & controller for dot matrix lcd fig-10. 6-dot font width cgrom/cgram 6) cursor or display shift (re = 0) shift right/left cursor position or display, without writing or reading of display data this instruction is used to correct or search display data.(refer to table 7) during 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. in 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. note that display shift is performed simultaneously in all the line. when displayed data is shifted repeatedly, each line shifted individually. when display shift is performed, the contents of address counter are not changed. table 11. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, address counter is decreased by 1 0 1 shift cursor to the right, address counter is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display 6-bit 8 - b i t cgrom character font (5-dot) s p a c e 6-bit 8 - b i t cgram character font (6-dot) (cgrom) (cgram) KS0075 34com/100seg driver & controller for dot matrix lcd 7) scroll enable (re = 1) ! ! ! ! ! & < <1 </ <& 8 5 ' 4 1 / & ! hs : horizontal scroll per line enable this instruction makes valid dot shift by a display line unit. hs1, hs2, hs3 and hs4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. if the line in 1-line display mode or the 1st line in 2-line display mode is to be scrolled, set hs1 and hs2 to "high". if the 2nd line scroll is needed in 2-line mode, set hs3 and hs4 to "high". (refer to table 8) 8) function set (re = 0) dl : interface data length control bit when dl = "high", it means 8-bit bus mode with mpu. when dl = "low", it means 4-bit bus mode with mpu. so to speak, dl is a signal to select 8-bit or 4-bit bus mode. in 4-bit bus mode, it is required to transfer 4-bit data. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", 1-line display mode is set. when n = "high", 2-line display mode is set. when nw = "high", n bit is invalid, it means 4-line mode independent of n bit. re : extended function registers enable bit at this instruction, re must be "low". KS0075 34com/100seg driver & controller for dot matrix lcd (re = 1) dl : interface data length control bit when dl = "high", it means 8-bit bus mode with mpu. when dl = "low", it means 4-bit bus mode with mpu. hence, dl is a signal to select 8-bit or 4-bit bus mode. in 4-bit bus mode, it is required to transfer 4-bit data twice. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", 1-line is set. when n = "high", 2-line display mode is set. when nw = "high", n bit is invalid, 4-line mode independent of n bit. re : extended function registers enable bit when re = "high", extended function set registers, segram address set registers, hs bits of scroll enable instruction and be bits of function set register can be accessed. be : cgram/segram data blink enable bit if be is "high", makes user font of cgram and segment of segram blinking. the quantity of blink is assigned the highest 2 bit of cgram/segram. 9) set cgram address (re = 0) set cgram address to ac. this instruction makes cgram data available from mpu. 10) set segram address (re = 1) set segram address to ac. this instruction makes segram data available from mpu. ' ( ! $ ! 8 5 ' 4 1 / & ! & & KS0075 34com/100seg driver & controller for dot matrix lcd 11) set ddram address (re = 0) set ddram address to ac. this instruction makes ddram data available from mpu. in 1-line display mode (n = 0, nw = 0), ddram address is from "00h" to "4fh". in 2-line display mode (n = 1, nw = 0), ddram address in the 1st line is from "00h" to "27h", and ddram address in the 2nd line is from "40h" to "67h". in 4-line display mode (nw = 1), ddram address is from "00h" to "13h" in the 1st line, from "20h" to "33h" in the 2nd line, from "40h" to "53h" in the 3rd line and from "60h" to "73h" in the 4th line. 12) set scroll quantity (re = 1) 8 5 ' 4 1 / & ! setting sq5 to sq0, horizontal scroll quantity can be controlled in dot units. (refer to table 12). in this case of KS0075 execute dot smooth scroll from 1 to 48 dots. table 12. scroll quantity according to hds bits sq5 sq4 sq3 sq2 sq1 sq0 function 0 00000 no shift 0 00001 shift left by 1-dot 0 00010 shift left by 2-dot 0 00011 shift left by 3-dot : ::::: : 1 01111 shift left by 47-dot 1 1xxxx shift left by 48-dot KS0075 34com/100seg driver & controller for dot matrix lcd 13) read busy flag & address this instruction shows whether KS0075 is in internal operation or not. if the resultant bf is high, it means the internal operation is in progress and should to wait until bf to become low. which by then the next instruction can be performed. in this instruction value of address counter can also be read. 14) write data to ram write binary 8-bit data to ddram/cgram/segram. the selection of ram from ddram, cgram, or segram, is set by the previous address set instruction : ddram address set, cgram address set, segram address set. ram set instruction can also determines the ac direction to ram. after write operation, the address is automatically increased/decreased by 1, according to the entry mode. 15) read data from ram read binary 8-bit data from ddram/cgram/segram. the selection of ram is set by the previous address set instruction. if address set instruction of ram is not performed before this instruction, the data that read first is invalid, as the direction of ac is not determined. if the ram data is read sever al times without ram address set instruction before read operation, the correct ram data from the second, but the first data would be incorrect, as there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram address set instruction : it also transfer ram data to output data register. after read operation address counter is automatically increased/decreased by 1 according to the entry mode. after cgram/segram read operation, display shift may not be executed correctly. * in case of ram write operation, ac is increased/decreased by 1 like read operation after this. in this time, ac indicates the next address position, but the previous data can only be read by read instruction. KS0075 34com/100seg driver & controller for dot matrix lcd interface with mpu KS0075 can transfer data in bus mode (4-bit or 8-bit) or serial mode with mpu. hence, both types of 4 or 8-bit mpu can be used. in case of 4-bit bus mode, data transfer is performed by twice to transfer 1 byte data. (1) when interfacing data length are 4-bit, only 4 ports, from db4 to db7, are used as data bus. at first higher 4-bit (in case of 8-bit bus mode, the contents of db4 - db7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of db0 - db3) are transferred. so transfer is performed by twice. busy flag outputs "high" after the second transfer is ended. (2) when interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from db0 to db7. (3) if im is set to "low", serial transfer mode is set. KS0075 34com/100seg driver & controller for dot matrix lcd interface with mpu in bus mode 1) interface with 8-bits mpu if 8-bits mpu is used, KS0075 can connect directly with that. in this case, port e, rs, r/w and db0 to db7 need to interface each other. example of timing sequence is shown below. fig 11. example of 8-bit bus mode timing sequence 2) interface with 4-bits mpu if 4-bits mpu is used, KS0075 can connect directly with this. in this case, port e, rs, r/w and db4 to db7 need to interface each other. the transfer is performed by twice. example of timing sequence is shown below. fig 12. example of 4-bit bus mode timing sequence rs r/w e db7 internal signal busy busy data data internal operation busy flag check busy flag check busy flag check instruction instruction no busy rs r/w e db7 internal signal busy internal operation busy flag check busy flag check instruction instruction no busy d3 d7 ac3 ac3 d3 d7 KS0075 34com/100seg driver & controller for dot matrix lcd interface with mpu in serial mode when im port input is "low", serial interface mode is started. at this time, all three ports, sclk (synchronizing transfer cloc k), sid (serial input data), and sod (serial output data), are used. if KS0075 is to be used with other chips, chip select port (cs) be used. by setting cs to "low", KS0075 can receive sclk input. if cs is set to "high", KS0075 reset the internal transfer counter. before transfer real data, start byte has to be transferred. it is composed of succeeding 5 "high" bits, read write control bit (r/w), register selection bit (rs), and end bit that indicates the end of start byte. whenever succeeding 5 "high" bits are detected by KS0075, it resets serial transfer counter and prepares to receive next information. the next input data are register selection bit which determine which register is to be used, and read write control bit that determine the direction of data. then end bit is transferred, which must have "low" value to show the end of start byte. (refer to fig 13. fig 14) (1) write operation (r/w = 0) after start byte is transferred from mpu to KS0075, 8-bit data is transferred which is divided into 2 bytes, each byte has 4 bit's real data and 4 bit's partition token data. for example, if real data is "10110001" (d0 - d7), then serially transferre d data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer. to transfer several bytes continuously without changing r/w bit and rs bit, start byte transfer is needed only at first startin g time. i.e., after first start byte is transferred, real data succeeding can be transferred. (2) read operation (r/w = 1) after start byte is transferred to KS0075, mpu can receive 8-bit data through the sod port at a time from the lsb. wait time is needed to insert between start byte and data reading, as internal reading from ram requires some delay. continuous data reading is possible such as serial write operation. it also needs only one start bytes, only if some delay betw een reading operations of each byte is inserted. during the reading operation, KS0075 observes succeeding 5 "high" from mpu. if detected, KS0075 restarts serial operation at once and prepares to receive rs bit. so in continuous reading operation, sid port must be "low". KS0075 34com/100seg driver & controller for dot matrix lcd fig 13. timing diagram of serial data transfer 12345678910111213141516 "1" "1" "1" "1" "1" "r/w" "rs""0" "0" "0" "0" "0" "0" "0" "0" "0" starting byte instruction starting byte read data (1) serial write operation (2) serial read operation cs "1""1""1""1""1" "r/w""rs" 0d0 d1d2d3"0""0""0""0" d4 d5 d6 d7 "0" "0" "0" "0" sid cs sclk sid d0 d1 d2 d3 d4 d5 d6 d7 in va lid dat a sod (input) (input) (input) synchronizing lower data 1'st byte upper data 2'nd byte (input) (input) (input) (output) synchronizing lower upper busy flag/ data data bit string bit string KS0075 34com/100seg driver & controller for dot matrix lcd fig 14. timing diagram of continuous data transfer (1) continuous write operation sclk 1st byte 2nd byte start byte (instruction1) 1st byte 2nd byte (instruction2) 1st byte 2nd byte (instruction3) instruction1 execution time instruction2 execution time instruction3 execution time sid start byte data read1 data read2 data read3 instruction1 execution time instruction2 execution time instruction3 execution time sclk sid sod (2) continuous read operation wait wait wait wait wait KS0075 34com/100seg driver & controller for dot matrix lcd application information according to lcd panel 1) lcd panel : 40 character x 1 line format (5-dot font,1/17 duty) 2) lcd panel : 40 character x 2 line format (5-dot font, 1/33 duty) KS0075 34com/100seg driver & controller for dot matrix lcd 3) lcd panel : 20 character x 4 line format (5-dot font, 1/33 bias) KS0075 34com/100seg driver & controller for dot matrix lcd 4) lcd panel : 16 character x 4 line format (6-dot font, 1/33 bias) ! "! KS0075 34com/100seg driver & controller for dot matrix lcd initializing 1) initializing by internal reset circuit when the power is turned on, KS0075 is initialized automatically by power on reset circuit. during the initialization, the following instructions are executed, and bf(busy flag) is kept "high"(busy state) to the end of initialization. display clear instruction write "20h" to all ddram set functions instruction dl = 1 : 8-bit bus mode n = 1 : 2-line display mode re = 0 : extension register disable be = 0 : cgram/segram blink off dh = 0 : horizontal scroll enable rev = 0 : normal display (not reversed display) control display on/off instruction d = 0 : display off c = 0 : cursor off b = 0 : blink off set entry mode instruction i/d = 1 : increment by 1 s = 0 : no entire display shift bid = 0 : normal direction segment port set extension function instruction fw = 0 : 5-dot font width character display b/w = 0 : normal cursor (8th line) nw = 0 : not 4-line display mode, 2-line mode is set because of n("1") enable shift instruction hs = 0000 : scroll per line disable ds = 0000 : shift per line disable set scroll quantity instruction sq = 000000 : not scroll 2) initializing by hardware reset input when reset pin = "low", KS0075 can be initialized like the case of power on reset. during the power on reset operation, this pin is ignored. KS0075 34com/100seg driver & controller for dot matrix lcd initializing by instruction 1) 8-bit interface mode power on wait for more than 20 ms after vdd rises to 4.5v wait for more than 39 m s wait for more than 39 m s wait for more than 1.53ms initialization end (dl=1) dl n 0 1 0 1 4-bit interface 8-bit interface 1-line mode 2-line mode 0 display off d c 1 0 1 display on cursor off cursor on 0 1 b blink off blink on 0 decrement mode i/d s 1 0 1 increment mode entire shift off entire shift on rs rw db6 db5 db4 db3 db2 db1 db0 0 001 dl (1) n0x x function set db7 0 rs rw db6 db5 db4 db3 db2 db1 db0 0 000 0 0 00 1 clear dsplay db7 0 rs rw db6 db5 db4 db3 db2 db1 db0 0 000 0 0 1i/ds entry mode set db7 0 rs rw db6 db5 db4 db3 db2 db1 db0 0 000 0 1 dc b dsplay on/off control db7 0 condition: 270 khz KS0075 34com/100seg driver & controller for dot matrix lcd 2) 4-bit interface mode power on wait for more than 20 ms after vdd rises to 4.5v wait for more than 39 m s rs rw db6 db5 db4 db3 db2 db1 db0 0 00 1 0 x xx x function set wait for more than 39 m s wait for more than 39 m s initialization end (dl=0) dl n 0 1 0 1 4-bit interface 8-bit interface 1-line mode 2-line mode 0 display off d c 1 0 1 display on cursor off cursor on 0 1 b blink off blink on 0 decrement mode i/d s 1 0 1 increment mode entire shift off entire shift on x xx x x x 0 0 n rs rw db6 db5 db4 db3 db2 db1 db0 0 001 dl (0) xxx x function set db7 0 db7 x 0 rs rw db6 db5 db4 db3 db2 db1 db0 0 000 0 x xx x dsplay on/off control 0 1dc bx xx x 0 0 db7 rs rw db6 db5 db4 db3 db2 db1 db0 0 000 0 x xx x clear dsplay 0 000 1x xx x 0 0 db7 wait for more than 1.53ms rs rw db6 db5 db4 db3 db2 db1 db0 0 000 0 x xx x entry modeset 0 i/d s xxx x 0 1 db7 00 condition: 270 khz KS0075 34com/100seg driver & controller for dot matrix lcd example of instruction and display correspondence 1) ie = "low" ! " # $ $ %& %'( ) ) *$ +,! - , - ./0 # 121** & # &# . 3 $4 '3 '3 ' '3 3 + '3 KS0075 34com/100seg driver & controller for dot matrix lcd ' '7 &0 & & & & & & & 89 7 :!" $ ! !# &&' 4 7 :!" ; ' '7 &0 & & & & & & & 9 7 :!" $ ! !# &&' 4 7 :!" < ' '7 &0 & & & & & & & 9 7 :!" $ ! !# &&' 4 7 :!" ) ' '7 &0 & & & & & & & 1 1 9 - *# # &:*3= > :?! 4 - *# * :?! !# :@ ! ' '7 &0 & & & & & & & 9 a,! > #$" "! 4 a,!: " $:*3= > * :?! ", /=" ' '7 &0 & & & & & & & 9 7 :!" $ ! !# &&' 4 7 :!" b ' '7 &0 & & & & & & & 9 7 :!" $ ! !# &&' 4 7 :!" ' '7 &0 & & & & & & & 9 7 :!" $ ! !# &&' 4 7 :!" KS0075 34com/100seg driver & controller for dot matrix lcd '3 + '3 5 '3 ) ) &# # " 6 &# #" 6 6 '3 ) 74 & # KS0075 34com/100seg driver & controller for dot matrix lcd 2) ie = "high" ' ) * + , - . / 0 0+ ) ' ) &+0 , "/ 1 %$ ' ) 2342&& 5 , 45+ ' ) &+0 , % $ ' ) ' , ' ' ) 6 &+0 , 1 KS0075 34com/100seg driver & controller for dot matrix lcd & ' ' ' ' ' ' ' ' 7. write data to ddram : write a rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 0 1 1 1 12. write data to ddram : write g rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 0 13. set ddram address 20h sa_ samsung _ samsung_ rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 1 0 1 1 14. write data to ddram : write k rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 1 1 0 1 0 1 19. write data to ddram : write 5 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 0 0 0 0 20. set ddram address 40h samsung k_ samsung KS0075 _ samsung KS0075_ KS0075 34com/100seg driver & controller for dot matrix lcd KS0075 34com/100seg driver & controller for dot matrix lcd KS0075 34com/100seg driver & controller for dot matrix lcd KS0075 34com/100seg driver & controller for dot matrix lcd KS0075 34com/100seg driver & controller for dot matrix lcd frame frequency 1) 1/17 duty cycle item display font width 5-dot font width 6-dot font width 1-line selection period 200 clocks 240 clocks frame frequency 79.4hz 66.2hz * fosc = 270 khz (1 clock = 3.7 m s) 2) 1/33 duty cycle item display font width 5-dot font width 6-dot font width 1-line selection period 100 clocks 120 clocks frame frequency 81.8hz 68.2hz fosc = 270 khz (1 clock = 3.7 m s) KS0075 34com/100seg driver & controller for dot matrix lcd power supply for driving lcd panel 1) when an external power supply is used 2) when an internal booster is used 1. boosted output voltage should not exceed the maximum value (13 v) of the lcd driving voltage. especially, a voltage of over 4.3v should not be input to the reference voltage (vci) when boosting three times. 2. a voltage of over 5.5v should not be input to the reference voltage (vci) when boosting twice. 3. the value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (refer to table 13) table 13. duty ratio and power supply for lcd driving item data number of lines 1 2 or 4 duty ratio 1/17 1/33 bias 1/5 1/6.7 divided resistance r r r r0 r 2.7r KS0075 34com/100seg driver & controller for dot matrix lcd maximum absolute rate characteristic symbol value unit power supply voltage (1) v dd -0.3 ~ +7.0 v power supply voltage (2) v lcd v dd -15.0 ~ v dd +0.3 v input voltage v in -0.3 ~ v dd +0.3 v operating temperature t opr -30 ~ +85 o c storage temperature t stg -55 ~ +125 o c voltage greater than above may damage to the circuit (vdd 3 v1 3 v2 3 v3 3 v4 3 v5) KS0075 34com/100seg driver & controller for dot matrix lcd electrical characteristics dc characteristics (vdd = 2.7v ~ 5.5v, ta=-30 ~ + 85 o c) characteristic symbol condition min typ max unit operating voltage v dd - 2.7 - 5.5 v supply current i dd internal oscillation or external clock. (v dd =3.0v,fosc=270khz) - 0.15 0.3 ma input voltage (1) v ih1 -0.7v dd -v dd (except osc1) v il1 v dd =2.7 to 3.0 -0.3 - 0.2v dd - v dd =3.0 to 5.5 -0.3 - 0.6 input voltage (2) v ih2 -0.7v dd -v dd v (osc1) v il2 ---0.2v dd output voltage (1) v oh1 i oh =-0.1 ma 0.75v dd --v (db0 to db7) v ol1 i ol =0.1 ma - - 0.2v dd output voltage(2) v oh2 i o =-40 m a 0.8v dd --v (except db0 to db7) v ol1 i o =40 m a - - 0.2v dd voltage drop vd com i o = 0.1ma --1v vd seg --1 input leakage current i lkg v in =0v to v dd -1 - 1 m a low input current i il v in =0v, v dd =3v (pull up) -10 -50 -120 internal clock (external rf) f osc rf=91[k w ] 2% (v dd =5v) 190 270 350 khz external clock f ec 125 270 410 khz duty - 45 50 55 % t r , t f --0.2 m s voltage converter out2 (vci = 4.5v) v out2 ta = 25 , c=1 m f, i out = 0.25ma, -3.0 -4.2 - v voltage converter out3 (vci = 2.7v) v out3 f osc =270khz -4.3 -5.1 - voltage converter input vci - 1.0 - 4.5 lcd driving voltage v lcd v dd -v5 1/5 bias 3.0 - 13.0 v 1/6.7 bias 3.0 - 13.0 KS0075 34com/100seg driver & controller for dot matrix lcd ac characteristics (v dd =4.5~ 5.5v, ta=-30 ~ +85 o c) mode item symbol min typ max unit e cycle time tc, 500 - - e rise / fall time t r , t f --20 e pulse width (high, low) tw 230 - - ns (1) write mode r/w and rs setup time tsu1 40 - - (refer to fig-15) r/w and rs hold time t h 110 - - data setup time tsu2 60 - - data hold time t h 210 - - e cycle time tc 500 - - e rise / fall time t r ,t f --20 e pulse width (high, low) tw 230 - - ns (2) read mode r/w and rs setup time tsu 40 - - (refer to fig-16) r/w and rs hold time t h 10 - - data output delay time t d - - 160 data hold time t dh 5- - serial clock cycle time tc 0.5 - 20 m s serial clock rise/fall time t r ,t f --50 serial clock width (high, low) tw 200 - - (3) serial chip select setup time tsu1 60 - - interface mode chip select hold time t h1 20 - - ns (refer to fig-17) serial input data setup time tsu2 100 - - serial input data hold time t h2 100 - - serial output data delay time t d - - 160 serial output data hold time t dh 5- - KS0075 34com/100seg driver & controller for dot matrix lcd ac characteristics (continued) (v dd =2.7 ~ 5.5v, ta=-30 ~ +85 o c) mode item symbol min typ max unit e cycle time tc, 1000 - - e rise / fall time t r , t f --25 e pulse width (high, low) tw 450 - - ns (4) write mode r/w and rs setup time tsu1 60 - - (refer to fig-15) r/w and rs hold time t h 120 - - data setup time tsu2 195 - - data hold time t h 210 - - e cycle time tc 1000 - - e rise / fall time t r ,t f --25 e pulse width (high, low) tw 450 - - ns (5) read mode r/w and rs setup time tsu 60 - - (refer to fig-16) r/w and rs hold time t h 20 - - data output delay time t d - - 360 data hold time t dh 5- - serial clock cycle time tc 1 - 20 m s serial clock rise/fall time t r ,t f --50 serial clock width (high, low) tw 400 - - (6) serial chip select setup time tsu1 60 - - interface mode chip select hold time t h 120 - - ns (refer to fig-17) serial input data setup time tsu2 200 - - serial input data hold time t h 2 200 - - serial output data delay time t d - - 360 serial output data hold time t dh 5- - KS0075 34com/100seg driver & controller for dot matrix lcd fig-15. write mode fig-16. read mode KS0075 34com/100seg driver & controller for dot matrix lcd fig-17. serial interface mode reset timing (v dd = 2.7 ~ 5.5v, ta = -30 ~ +85 o c) item symbol min typ max unit reset low level width (refer to fig-18) t res 10 - - ms |
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